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n-channel 100v - 0.110 ? - 3a so-8 p-channel 100v - 0.320 ? - 1.5a so-8 complementary pair stripfet? power mosfet 1/11 june 2004 . STS3C2F100 rev.1.0.1 typical r ds (on) (n-channel) = 0.110 ? typical r ds (on) (p-channel) = 0.320 ? standard outline for easy automated surface mount assembly ultra low gate charge ultra low on-resistance description this mosfet is the second generation of stmicroelec- tronis unique "single feature size?" strip-based pro- cess. the resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. applications dc motor drives audio amplifier ordering information type v dss r ds(on) i d STS3C2F100(n-channel) STS3C2F100(p-channel) 100 v 100 v < 0.145 ? < 0.380 ? 3.0 a 1.5 a sales type marking package packaging STS3C2F100 s3c2f100 so-8 tape & reel so-8 absolute maximum ratings ( ?) pulse width limited by safe operating area. note: p-channel mosfet actual polarity of voltages and current has to be reversed symbol parameter n-channel p-channel unit v ds drain-source voltage (v gs = 0) 100 v v dgr drain-gate voltage (r gs = 20 k ? ) 100 v v gs gate- source voltage 20 v i d drain current (continuous) at t c = 25c 3.0 1.5 a i d drain current (continuous) at t c = 100c 1.9 1.0 a i dm ( ?) drain current (pulsed) 12 6 a p tot total dissipation at t c = 25c 2w t stg storage temperature -55 to 150 c t j max. operating junction temperature 150 c internal schematic diagram
STS3C2F100 2/11 tab.1 thermal data (1) when mounted on 1 in 2 pad of 2 oz. copper, t 10sec. electrical characteristics (t j = 25 c unless otherwise specified) tab.2 off tab.3 on tab.4 dynamic rthj-amb (1) thermal resistance junction-ambient 62.5 c/w symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 n-ch p-ch 100 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125c n-ch p-ch 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v n-ch p-ch 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a n-ch p-ch 2 2 v v r ds(on) static drain-source on resistance v gs = 10 v i d = 1.5 a v gs = 10 v i d = 1.0 a n-ch p-ch 0.110 0.320 0.145 0.380 ? ? symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds = 20 v i d = 1.5 a v ds = 30 v i d = 1.0 a n-ch p-ch 3 4 s s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 n-ch p-ch n-ch p-ch n-ch p-ch 460 705 70 83 30 30 pf pf pf pf pf pf
3/11 STS3C2F100 tab.5 switching on tab.6 switching off tab.7 source drain diode ( ?) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( ?) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time n-channel v dd = 50 v i d = 1.5 a r g =4.7 ? v gs = 10 v p-channel v dd = 50 v i d = 1.5 a r g =4.7 ? v gs = 10 v (resistive load, figure 1) n-ch p-ch n-ch p-ch 16 14 25 20 ns ns ns ns qg q gs q gd total gate charge gate-source charge gate-drain charge n-channel v dd =80v i d =3a v gs =10v p-channel v dd = 80v i d = 1.5a v gs = 10v (see test circuit, figure 2) n-ch p-ch n-ch p-ch n-ch p-ch 15 20 3.7 2.0 4.7 6.0 20 27 nc nc nc nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time n-channel v dd = 50 v i d = 1.5 a r g =4.7 ? v gs = 10 v p-channel v dd = 50 v i d = 1.5 a r g =4.7 ? v gs = 10 v (resistive load, figure 1) n-ch p-ch n-ch p-ch 32 33 20 7.5 ns ns ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ?) source-drain current source-drain current (pulsed) n-ch p-ch n-ch p-ch 3.0 1.5 12 6.0 a a a a v sd ( ?) forward on voltage i sd = 3 a v gs = 0 i sd = 1.5 a v gs = 0 n-ch p-ch 1.2 1.2 v v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current n-channel i sd = 3 a di/dt = 100a/ s v dd =50 vt j =150 o c p-channel i sd = 1.5 a di/dt = 100a/ s v dd =50 vt j =150 o c (see test circuit, figure 3) n-ch p-ch n-ch p-ch n-ch p-ch 90 65 230 175 5.0 5.4 ns ns nc nc a a electrical characteristics (continued)
STS3C2F100 4/11 safe operating area n-ch thermal impedance n-ch output characteristics n-ch transfer characteristics n-ch transconductance n-ch static drain-source on resistance n-ch
5/11 STS3C2F100 gate charge vs gate-source voltage n-ch capacitance variations n-ch normalized gate threshold voltage vs temperature n-ch normalized on resistance vs temperature n-ch source-drain diode forward characteristics n-ch normalized breakdown voltage vs temperature n-ch
STS3C2F100 6/11 safe operating area p-ch thermal impedance p-ch output characteristics p-ch transfer characteristics p-ch transconductance p-ch static drain-source on resistance p-ch
7/11 STS3C2F100 gate charge vs gate-source voltage p-ch capacitance variations p-ch normalized gate threshold voltage vs temperature p-ch normalized on resistance vs temperature p-ch source-drain diode forward characteristics p-ch normalized breakdown voltage vs temperature p-ch
STS3C2F100 8/11 fig. 2: gate charge test circuit fig. 3: test circuit for diode recovery behaviour fig. 1: switching times test circuits for resistive load
9/11 STS3C2F100 dim. mm inch min. typ. max. min. typ. max. a1.750.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m0.60.023 s8 (max.) 0016023 so-8 mechanical data
STS3C2F100 10/11 revision history date revision description of changes friday 18 june 2004 1.0.1 first issue
11/11 STS3C2F100 i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express writte n approval of stmicroelectron ics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco -singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com

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